The present disclosure relates to methods for manufacturing a nonvolatile semiconductor memory device, and more particularly to methods for manufacturing a nonvolatile semiconductor memory device having both a storage (memory) section and a logic section including, e.g., a complementary metal oxide semiconductor (CMOS) device.
With miniaturization of elements, nonvolatile semiconductor memory devices, having both a memory section and a logic section (a CMOS section) on a semiconductor substrate, and using an oxide-nitride-oxide (ONO) film (a stacked film of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film) as respective gate insulating films of memory transistors of the memory section, are becoming increasingly important.
A conventional nonvolatile semiconductor memory device having both a memory section and a CMOS section will be described below with reference to the accompanying drawings (see, e.g., Japanese Published Patent Application No. 2001-077220).
FIGS. 11A-11B and 12A-12C show a conventional nonvolatile semiconductor memory device. FIG. 11A shows a planar configuration of a memory section, and FIG. 11B shows a planar configuration of a CMOS section. Silicide layers 106 are not shown in FIGS. 11A and 11B. FIG. 12A shows a cross-sectional configuration taken along line A-A in FIG. 11A, FIG. 12B shows a cross-sectional configuration taken along line B-B in FIG. 11A, and FIG. 12C shows a cross-sectional configuration taken along line C-C in FIG. 11B.
As shown in FIGS. 11A, 12A, and 12B, in the memory section, bit line diffusion layers 102 are formed in the upper part of a silicon semiconductor substrate 101, and bit line insulating films 103 are respectively formed on the bit line diffusion layers 102. A plurality of control gate electrodes 104a as word lines are formed on the bit line insulating films 103 so that each control gate electrode 104a crosses corresponding ones of the bit line diffusion layers 102. A gap fill insulating film 105 is formed between adjoining ones of the control gate electrodes 104a, and silicide layers 106 are respectively formed on the control gate electrodes 104a. 
As shown in FIG. 12B, a bit line contact region 120 between the bit line diffusion layers 102 of the same row is isolated by shallow trench isolation (STI) insulating films 107 in the column direction. The bit line contact region 120 is a region where a contact 115 is to be formed. The bit line contact region 120 is formed by a connection diffusion layer 108 formed in the upper part of the semiconductor substrate 101, and a silicide layer 106 formed on the connection diffusion layer 108. As shown in FIG. 12A, the connection diffusion layer 108 is formed so as to electrically connect the bit line diffusion layers 102 located on both sides of the connection diffusion layer 108.
As shown in FIGS. 11B and 12C, in the CMOS section, a gate insulating film 109 is formed on the silicon semiconductor substrate 101, and a gate electrode 104c is formed on the gate insulating film 109. Source/drain diffusion layers 110 are respectively formed in regions located on both sides of the gate insulating film 109 and the gate electrode 104c in the upper part of the semiconductor substrate 101. Silicide layers 106 are respectively formed on the gate electrode 104c and the source/drain diffusion layers 110.
A method for manufacturing the conventional nonvolatile semiconductor memory device will be described below with reference to the drawings.
FIGS. 13A-19C are a series of cross-sectional views illustrating the method for manufacturing the conventional nonvolatile semiconductor memory device. FIGS. 13A, 14A, 15A, 16A, 17A, 18A, and 19A show cross-sectional configurations taken along line A-A in FIG. 11A. FIGS. 13B, 14B, 15B, 16B, 17B, 18B, and 19B show cross-sectional configurations taken along line B-B in FIG. 11A. FIGS. 13C, 14C, 15C, 16C, 17C, 18C, and 19C show cross-sectional configurations taken along line C-C in FIG. 11B. That is, FIGS. 13A-13B, 14A-14B, 15A-15B, 16A-16B, 17A-17B, 18A-18B, and 19A-19B show the memory section, and FIGS. 13C, 14C, 15C, 16C, 17C, 18C, and 19C show the CMOS section.
First, as shown in FIGS. 13A-13C, STI insulating films 107 are formed in the upper part of a silicon semiconductor substrate 101 so as to isolate adjoining ones of bit line contact regions 120 from each other.
Next, as shown in FIGS. 14A-14C, an ONO film 111 is formed over the entire surface of the semiconductor substrate 101 in the memory section and the CMOS section. The ONO film 111 is a stacked film of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film. Then, in the memory section, regions of the ONO film 111 for forming bit line diffusion layers 102 are removed, and the bit line diffusion layers 102 are formed in the upper part of the exposed semiconductor substrate 101. Thereafter, bit line insulating films 103 are respectively formed on the bit line diffusion layers 102. Then, the ONO film 111 in the CMOS section is removed, and a gate insulating film 109 is formed on the semiconductor substrate 101. Subsequently, a polysilicon film 104 is deposited over the entire surface of the memory section and the CMOS section by a chemical vapor deposition (CVD) method.
As shown in FIGS. 15A-15C, a mask pattern 112 for forming control gate electrodes is formed in the memory section by a photolithography method. The polysilicon film 104 is etched by using the mask pattern 112, thereby forming control gate electrodes 104a from the polysilicon film 104.
As shown in FIGS. 16A-16C, after the mask pattern 112 is removed, a gap fill insulating film 105 is deposited on the entire surface of the memory section and the CMOS section by a CVD method.
As shown in FIGS. 17A-17C, the deposited gap fill insulating film 105 is etched back by a dry etching method until the control gate electrodes 104a are exposed.
As shown in FIGS. 18A-18C, a mask pattern 113 for forming gate electrodes is formed in the CMOS section by a photolithography method. The polysilicon film 104 is etched by using the mask pattern 113, thereby forming a gate electrode 104c from the polysilicon film 104.
As shown in FIGS. 19A-19C, after the mask pattern 113 is removed, a connection diffusion layer 108 is formed between adjoining ones of the bit line diffusion layers 102 in the semiconductor substrate 101 in the memory section. Source/drain diffusion layers 110 are formed on both sides of the gate insulating film 109 and the gate electrode 104c in the semiconductor substrate 101 in the CMOS section. Then, silicide layers 106 are respectively formed on the control gate electrodes 104a, the connection diffusion layer 108, the gate electrode 104c, and the source/drain diffusion layers 110.